This invention relates to a semiconductor device and a method for fabricating the semiconductor device, which is particularly suitable for fabricating a semiconductor memory device.
More particularly, this invention relates to a structure of a semiconductor device and a method for fabricating such a semiconductor device, which is obtained by utilizing a self aligned contact (SAC) technique for forming a contact hole above each active region of the semiconductor device. A DRAM device or the like obtained by this invention shows little or no degradation of data retention characteristics.
A method of fabricating a DRAM according to a design rule of approximately 3 xcexcm is described as an example in order to illustrate a conventional method of fabricating a semiconductor device using the SAC technique. FIGS. 21 to 40 are, respectively, sectional views for illustrating a conventional method of fabricating a DRAM.
Reference is now made to FIG. 21. Initially, a silicon semiconductor substrate 1 is entirely formed with an approximately 100 angstroms thick silicon thermal oxidation film 2 thereon by thermal oxidation, which is followed by further deposition of an approximately 500 angstroms thick silicon nitride film 3 by CVD. Subsequently, using photomechanical and etching techniques, the silicon nitride film 3 is selectively left only in regions wherein an element is to be formed.
Referring to FIG. 22, a thermal oxidation film 4 is selectively formed between the nitride films 3 with a thickness of approximately 3000 angstroms by thermal oxidation to provide an element separation oxide film, which is followed by removal of the nitride films 3 to form an element-forming region. In the figure, the left-side half indicates a memory cell portion A and the right-side half indicates a peripheral circuit portion B.
Next, a thermal oxidation film 5 which serves as a gate oxide film of a transistor is formed with a thickness of approximately 90 angstroms by thermal oxidation. Thereafter, phosphorus-doped polysilicon film 6 wherein phosphorus (P) is doped at a concentration of approximately 5xc3x971020 atoms/cm3, and tungsten silicide film (WSi2) 7 are, respectively, deposited with a thickness of approximately 500 angstroms by CVD to form a double-layered film 8 (which may be hereinafter referred to simply as a polyside).
Further, a silicon nitride film 27 is formed with a thickness of approximately 1000 angstroms by CVD. The silicon nitride film 27 serves as an etching mask at the time of the formation of a polyside gate and also as a stopper at the time of making holes for SAC. It will be noted that in FIGS. 22 to 40, the reference numeral 1 indicating the semiconductor substrate is, for convenience, not shown.
In FIG. 23, the nitride film 27 is subjected to photomechanical and anisotropic etching to leave desired portions of the nitride film 27 in a pattern. The polyside film 8 is anisotropically etched through the pattern of the nitride film 27 to form gate electrodes 8 with a gate length of approximately 0.3 xcexcm. The polyside film 8 is etched to extend just above the gate oxide film 5 as shown.
Subsequently, phosphorus ions are self-alignedly implanted into the respective gate electrodes 8 and the element separation oxide films 4 at a concentration of approximately 1xc3x971013 atoms/cm2 by an ion implantation, thereby forming lightly doped source/drain regions of a MOS transistor, i.e. so-called n-source/drain regions 10a, 10b, 10c and 10d. In the figure, the source/drain region 10a is connected with a bit line through a contact hole in a subsequent step, and the source/drain region 10b is connected with a lower electrode of a capacitor through another contact hole in a subsequent step.
Referring to FIG. 24, a silicon nitride film 11 is deposited with a thickness of approximately 800 angstroms by CVD. The nitride film 11 serves as side walls of a transistor having an LDD structure.
In FIG. 25, the silicon nitride film 11 is anisotropically etched to leave side walls 11a of the nitride film at the side walls of each gate electrode 8. The width, W1, of the side wall 11a is approximately 800 angstroms. It should be noted that the thin gate oxide film 5 does not act as a stopper for the anisotropic etching of the nitride film, but is readily removed by over-etching, thereby causing the source/drain regions 10a, 10b to be exposed.
In FIG. 26, the memory cell portion A is covered with a resist 12 according to a photomechanical technique. Using ion implantation, the gate electrode 8, the element separation oxide film 4 and the side walls 11a of the nitride film are self-alignedly implanted with arsenic at a concentration of approximately 5xc3x971015 atoms/cm2, respectively, thereby forming a heavily doped source/drain region, i.e. a so-called n+ source/drain region 13, of the MOS transistor.
At that time, the memory cell portion A has been covered with the resist 12, so that such an n+ source/drain region as mentioned above is prevented from being formed in the memory cell portion A. In the event that the n+ source/drain region is formed in the memory cell portion A, junction leakage current increases to degrade data retention characteristics. Accordingly, only the lightly doped nxe2x88x92 source/drain regions are formed in the memory cell portion A.
In FIG. 27, the resist 12 is removed from the memory cell portion A, and an oxide film containing boron and phosphorus (hereinafter referred to simply as BPSG) is deposited with a thickness of approximately 4000 angstroms by CVD, thereby forming an interlayer insulating film 14.
It should be noted here that in the above case, it is not appropriate to use an oxide film which is free of any boron or phosphorus, e.g. an TEOS oxide film. This is because an oxide film free of boron or phosphorus exhibits only a small selection ratio relative to the nitride film used as an etching stopper at the time of making a hole for SAC.
Referring to FIG. 28, the thermal treatment is carried out in an atmosphere of nitrogen at approximately 850xc2x0 C. for 20 minutes, by which the BPSG is thermally sagged to make the layer insulating film 14 flat on the surface thereof. At that time, the oxide film 14 at a portion where SAC is to be formed between the gate electrodes 8 has a thickness, t1, of approximately 6000 angstroms.
In FIG. 29, bit line contact holes 15 each having a diameter of approximately 0.3 xcexcm are, respectively, formed above the source/drain 10a of the memory cell portion A and the source/drain region 10c of the peripheral circuit portion B according to photomechanical and anisotropic oxide film-dry etching techniques. Each hole 15 is formed to connect a bit line and an active region therewith. At the time of the formation of the contact holes 15, the BPSG is over-etched by 30% which corresponds to a thickness of 9000 angstroms of the BPSG. Because the etching rate of the nitride film is about {fraction (1/20)} of that of BPSG, the nitride film 27 located above the source/drain region 10a of the memory cell portion is etched by a thickness, t2, of approximately 250 angstroms.
In FIG. 30, as in the case of the gate electrodes 8, a polyside layer 18 composed of a phosphorus-doped polysilicon film 16 and a tungsten silicide (WSi2) film 17 is deposited by CVD to fill the bit line contact hole therewith, followed by formation of a desired pattern by photomechanical and anisotropic dry etching techniques to form polyside interconnections 18. The line width, W2, of the polyside interconnection 18 is in the range of approximately 0.3 to 0.5 xcexcm, and the interconnections serve as a bit line of a DRAM and are, respectively, connected via the bit line contact holes 15 to the source/drain regions 10a, 10c. 
In FIG. 31, an approximately 3000 angstroms thick silicon oxide film is deposited over the substrate by CVD to form an interlayer insulating film 19.
In FIG. 32, a storage node contact hole 20 having a diameter of approximately 0.3 xcexcm is formed above the source/drain region 10b of the memory cell portion according to photomechanical and anisotropic oxide film dry etching techniques. This hole 20 is a contact hole for connection between a lower electrode of a capacitor (hereinafter referred to as a storage node) and the active region 10b. 
Referring to FIG. 33, after deposition of an approximately 7000 angstroms thick phosphorus-doped polysilicon film wherein phosphorous is doped at a concentration of approximately 5xc3x971020 atoms/cm3, the phosphorus-doped polysilicon film is subjected to photomechanical and anisotropic dry etching techniques in a desired pattern to form storage nodes 21. The space, W3, between the storage nodes 21 should be as small as possible in order to make a large surface area of the storage nodes 21, and is usually approximately 0.25 xcexcm. These respective storage nodes 21 are connected via the storage node contact holes 20 to the nxe2x88x92 source/drain regions 10b of the memory cell portion A.
In FIG. 34, a nitride film 22 serving as a capacitor dielectric film is deposited with a thickness of 60 angstroms, and then a phosphorus-doped polysilicon film 23 doped at a concentration of approximately 5xc3x971020 atoms/cm3 is deposited with a thickness of 1000 angstroms, and is used as an upper electrode 23 of a capacitor (hereinafter referred to as cell plate). The phosphorus-doped polysilicon film 23 formed in portions other than the memory cell portion A is removed by photomechanical and anisotropic dry etching techniques to form a cell plate 23, thereby completing a capacitor.
In FIG. 35, BPSG is deposited with a thickness of approximately 5000 angstroms by CVD to form an interlayer insulating film 24.
In FIG. 36, as in the case of the interlayer insulating film 14, thermal treatment is carried out in an atmosphere of nitrogen at about 850xc2x0 C. for about 30 minutes to make a smooth surface profile of the interlayer insulating film 24.
In FIG. 37, contact holes 25a each having a diameter of 0.3 to 0.4 xcexcm are, respectively, formed above and to the depth of the source/drain 10d of the peripheral circuit portion B and also above and to the depth of the bit line 18 formed in the peripheral circuit portion B by photomechanical and anisotropic oxide film dry etching techniques. The contact to the gate electrode 8 of the peripheral circuit portion B cannot be simultaneously formed, since the nitride film 27 is formed on the gate electrode 8, so that the etching of the oxide film is stopped at the nitride film 27.
In FIG. 38, a gate contact hole 25b is formed above the gate electrode 8 of the peripheral circuit portion B. In the figure, a hole has been made to the nitride film 27 by anisotropic dry etching.
Thereafter, as shown in FIG. 39, the nitride film is further etched from the gate contact hole 25b to make a hole in the nitride film 27 so that the upper surface of the gate electrode 8 is exposed.
In FIG. 40, aluminum film 26 is deposited with a thickness of approximately 5000 angstroms by sputtering to fill the contact holes 25a, 25b therewith, followed by patterning by photomechanical and anisotropic dry etching techniques to leave desired portions of the aluminum film, thereby forming aluminum interconnections 26 each having a width of approximately 0.4 xcexcm.
The conventional fabrication method of DRAM by use of the SAC technique has been described above. According to this method, the source/drain regions 10b are contacted with the storage nodes 21 after the formation of the storage node contact holes 20 in the memory cell portion A. During the course of the step of anisotropically etching the nitride film to form the side walls 11a made of the nitride film as shown in FIG. 25, the source/drain regions 10b are damaged by the etching, thus leading to considerable degradation of data retention characteristics.
In the peripheral circuit portion B, the silicon nitride film 27 is formed on the gate electrode 8, so that the formation of the contact holes undesirably requires two steps including the step of forming the contact hole 25a above the source/drain region 10d and the bit line 18, and the step of forming the contact hole 25b above the gate electrode 8.
Accordingly, an object of the present invention is to provide a semiconductor device and a method for fabricating the same using the SAC technique, which overcome the drawbacks of the conventional art and which involve little or no degradation of data retention characteristics, and which further reduces the fabrication steps.
According to one aspect of the present invention, in a method for fabricating a semiconductor device, a first insulating film is formed on a main surface of a silicon semiconductor substrate including a memory cell-forming portion and a peripheral circuit-forming portion. A first conductive layer is formed on said first insulating film. A silicon oxide film is formed on said first conductive layer. Said silicon oxide film and said first conductive layer are subjected to patterning to form a plurality of gate electrodes each having the silicon oxide film thereon. An impurity is introduced into the main surface of said semiconductor substrate at portions between any adjacent gate electrodes to form a plurality of active regions. A silicon nitride film is formed over the entire surface of said semiconductor substrate including said first insulating film and the plurality of gate electrodes. Said silicon nitride film in a peripheral circuit-forming portion of said semiconductor substrate is anisotropically etched to form side walls of said silicon nitride film on the side surfaces of each gate electrode. Simultaneously, a second insulating film is formed on the entire surface of said semiconductor substrate including said silicon nitride film of said memory cell-forming portion, and said silicon oxide film on each gate electrode, and the side walls of said silicon nitride film in the peripheral circuit-forming portion. Holes are made in said second insulating film, each between a pair of gate electrodes selected among the plurality of gate electrodes in said memory cell-forming portion. Further, the holes are extended from the first-mentioned holes to said silicon nitride film which is formed on said first insulating film and also to said first insulating film between the silicon nitride films which are formed on the side surfaces of the adjacent gate electrodes. Thereby, contacts arriving at the selected active regions are formed respectively. A hole is made in said second insulating film and said silicon oxide film on the gate electrode to form a contact extending to the gate electrode in the peripheral circuit-forming portion. Simultaneously, holes are made in said second insulating film on the active regions of said semiconductor substrate to form contacts extending to said active regions respectively.
In the above description, a method for fabricating a memory cell-forming portion of the semiconductor device is summarized as follows. First, a first insulating film is formed on a main surface of a silicon semiconductor substrate. A first conductive layer is formed on said first insulating film. A silicon oxide film is formed on said first conductive layer. Said silicon oxide film and said first conductive layer is subjected to patterning to form a plurality of gate electrodes each having said oxide film on the upper surface. An impurity is introduced into the main surface of said semiconductor substrate at portions between adjacent gate electrodes to form a plurality of active regions. A silicon nitride film is formed over the entire surface of said semiconductor substrate including said first insulating film and said plurality of gate electrodes. A second insulating film is formed on said silicon nitride film. Holes are made in said second insulating film, each between the adjacent gate electrodes selected among the plurality of gate electrodes. Further the holes are extended from the first-mentioned holes to said silicon nitride film which are formed on said first insulating film and also to said first insulating film between the silicon nitride films which are formed on the side surfaces of the adjacent gate electrodes. Thereby, contacts arriving at the selected active regions are formed.
In the above description, a method for fabricating a peripheral circuit-forming portion of the semiconductor device is summarized as follows. First, a first insulating film is formed on a main surface of a silicon semiconductor substrate. A first conductive layer is formed on said first insulating film. A first silicon oxide film is formed on said first conductive layer. Said silicon oxide film and said first conductive layer are subjected to patterning to form a plurality of gate electrodes each having said silicon oxide film on the upper surface. An impurity is introduced into the main surface of said semiconductor substrate at portions between any adjacent gate electrodes to form a plurality of active regions. A silicon nitride film is formed over the entire surface of said semiconductor substrate including said first insulating film and said plurality of gate electrodes. Said silicon nitride film is anisotropically etched to form side walls of the silicon nitride film on the side surfaces of each gate electrode. A second insulating film is formed over the entire surface of said semiconductor substrate including said silicon oxide film of the plural gate electrodes and the side walls of said silicon nitride film. A hole is made in said second insulating film and said silicon oxide film which is formed on each gate electrode to form a contact extending to said gate electrode. At the same time, another hole is formed in said second insulating film on each active region of said semiconductor substrate to form a contact extending to said each active region.
In another aspect of the present invention, in the method for fabricating a semiconductor device, said second insulating film is formed of silicon oxide.
In another aspect of the present invention, in the method for fabricating a semiconductor device, said first insulating film is formed of silicon oxide.
According to another aspect of the present invention, a semiconductor device comprises a plurality of active regions formed on a main surface of a semiconductor substrate having a memory cell portion and a peripheral circuit portion. A first insulating film is formed between individual pairs of active regions. A first conductive layer is formed on said first insulating film. A silicon oxide film is formed on said first conductive layer. A plurality of gate electrodes are then formed by pattering of said silicon oxide film and said first conductive layer.
Said memory cell portion comprises a silicon nitride film formed on the entire surface of said semiconductor substrate to cover said silicon oxide film and said first conductive film. A second insulating film is formed on said silicon nitride film. A contact is formed between any adjacent gate electrodes and between the silicon nitride films formed on the side surfaces of the adjacent gate electrodes, and extends to the active region via said second insulating film, said silicon nitride film formed on said fist insulating film, and said first insulating film.
The peripheral circuit portion comprises a silicon nitride film formed on side surfaces of said conductive film, a second insulating film formed on an entire surface of said semiconductor substrate to cover said silicon oxide film and said silicon nitride film. A contact is formed above each gate electrode, and extends via said second insulating film and said silicon oxide film to the gate electrode. Another contact is formed above the active region, and extends via said insulating film and said first insulating film to said active region.
In another aspect of the present invention, in the semiconductor device, said active region is constituted as source/drain of a MOS transistor.
In another aspect of the present invention, in the semiconductor device, said contact of said memory cell portion is formed as a contact with a bit line of said memory cell or as a contact with a storage node.
Additional advantages, advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.